Projects

EE581 - Mathematical Foundations for Systems Design: Modeling, Analysis, and Synthesis

Reverse Engineering of Sequential Circuits Using SAT Solving and Reduced Order Binary Decision Diagrams

The reliance on off-the-shelf logic components and IP cores outsourced from third-party vendors presents increased security concerns in modern System-on-Chip (SoC) development, where hidden malicious logic known as Hardware Trojans may remain undetected from examining the circuit-level design. To address these concerns, we propose a reverse engineering methodology for recovering the functional specification of a given gate-level sequential circuit in finite-state machine (FSM) representation. We demonstrate that the methodology accurately and efficiently reconstructs the FSM state space and next-state logic (NSL) of the underlying control logic, thus allowing the user to obtain the behavioral description of a given gate-level synthesized netlist and validate its high-level specification to identify design flaws and/or hidden malicious intent from external sources.

EE577A - VLSI System Design

Full Custom Design of RISC 5 Stage Pipelined 1.7GHz Microprocessor in 45 nm Technology Using Cadence Virtuoso

Schematic and layout design of an efficient general-purpose CPU that supports simple instructions such as Add, Bitwise operations, Store Word, and Load Word. A simple structure of the CPU contains Decoding Logic, Register File, Execution Units, Memory, and other surrounding circuitries. Our implementation includes datapath optimizations to reduce area, interally forwarding register file to reduce NOP/datapath stalling, True Single-Phase Clock (TSPC) Flip-Flops to replace DFF resulting in a 16T area savings, dual-VDD for power reduction, and logical effort for combinational logic optimal sizing and delay.

Github Link

EE597 - Wireless Networks

Saturation Throughput of IEEE 802.11 CSMA/CA in NS-3 / MATLAB

The objective of the project was to simulate the normalized saturation throughput of 802.11's CSMA/CA binary exponential backoff mechanism. We did this using NS3, and we compared our results to Bianchi's results. We also provide Analytical results that were produced in MATLAB We compare our simulation results with our analytical results as well.

Github Link

EE459 - Embedded Systems Design Laboratory (Capstone)

A New and Safer Electric Scooter Experience

The objective given was to develop a “smart” device that could enhance a recreational activity. Our cross-functional team, comprised of electrical engineering, marketing, and 3D CAD, chose to develop a “smart” scooter that increased the rider’s safety. Our product was also required to consider its ergonomics, ease-of-use, expandability, and reliability. For the project, I was the hardware design lead responsible for all schematic design relating to safety feature implementation.

Github Link

EE450 - Computer Networks

Socket Programming Project in C++

Many network related applications require fast identification of the shortest path between a pair of nodes to optimize routing performance. Given a weighted graph 𝐺(𝑉,𝐸) consisting of a set of vertices 𝑉 and a set of edges 𝐸, we aim at finding the path in 𝐺 connecting the source vertex 𝑣1 and the destination vertex 𝑣𝑛, such that the total edge weight along the path is minimized. This project Implemented a distributed system to compute the shortest path between server and client using Dijkstra’s algorithm while establishing TCP/UDP communication between client and servers using UNIX socket programming in C++.

Github Link

EE454 - Introduction to System-On-Chip

Hardware Acceleration of Convolutional Neural Networks for Drowsy Driving

Over the past few years, Convolutional Neural Networks (CNN) have been successfully used in many image recognition applications. CNN image and pattern recognition capabilities can be applied to the prevention and detection of drowsy driving. The operation of commercial and passenger vehicles while drowsy, fatigued, or asleep is a dangerous problem in the United States. In this paper, the CNN OpenCV eye detection algorithm will be implemented to indicate when a driver is entering a drowsy state. The bottlenecks in execution are identified using the runtime performance in Python. A 3x3 mesh-based NoC architecture is implemented in Verilog to facilitate hardware acceleration using parallelization.

Github Link